1. Field of the Invention
This invention relates to an arrangement for an emitter-coupled logic (ECL) gate or for a current mode logic (CML) gate which permits the series gating of several levels of binary logic and, more particularly, relates to a current source arrangement which requires a low voltage drop thereby allowing a sufficient voltage between V.sub.CC and ground to implement three-level ECL and four-level CML.
2. Discussion of Background and Prior Art
As the densities of integrated circuits have increased, the limits of physics, fabrication equipment and process technique are being reached. To further enhance the capability of integrated circuits to perform logic functions, a number of additional steps have been taken or are being considered. A first approach is to use logic schemes of higher order than binary. Thus ternary or quaternary logic has been used. For such higher order logic there are three or four discrete states, respectively, which are permissible on each output line. See, e.g., K. W. Current et al., "Implementing Parallel Counters with Four-Valued Threshold Logic", IEEE Transactions on Computers, v. C-28, No. 3, March 1979, p. 200; and K. W. Current, "High Density Integrated Computing Circuitry With Multiple Valued Logic", IEEE J. of Solid-State Circuits, v. SC-15, No. 1, February 1980, p. 127.
Another approach has been the use of input lines and output lines interchangeably, i.e., input and output lines have been multiplied, thereby reducing the number of pins required on packaged integrated circuits. This has also permitted the use of a generalized integrated circut such as a programmable read only memory (PROM) for a large number of different, specific applications.
A further approach to obtaining enhanced logic performance out of a given integrated circuit or a given amount of silicon has been the use of series gated devices or Cascode logic. Here, at least two levels of binary logic are stacked on each other. At times, three levels are possible. See, e.g., R. J. Scavuzzo, "EFL Logic Arrays", U.S. Pat. No. 4,378,508; and G. L. Baldwin et al., "Modular, High-Speed Serial Pipeline Multiplier for Digital Signal Processing", IEEE J. of Solid State Circuits, v. SC-13, no. 3, p. 400, June 1978. Two level ECL has been used for commercial bipolar integrated circuits such as the Advanced Micro Devices 2901 Bit Slice Microprocessor and the Advanced Micro Devices 29116 16 Bit Microprocessor. In such applications a significant increase in logic is obtained with no increase in production cost. The benefits are obtained because the peripheral devices such as output transistors and input transistors in a given device are shared for each level of logic. More logic functions are performed for a given amount of power consumption, less delay is experienced and less silicon area is required. Similar and additional advantages would accrue if three-level ECL could be accomplished. The barrier to obtaining three-level ECL, as described in detail subsequently, is that power supplies are specified at set voltage values and each level of logic consumes a certain voltage span and the conventional current source takes up so much voltage that only two levels of logic are possible. The voltage span between V.sub.CC and V.sub.EE, (V.sub.CC -V.sub.EE), is accounted for without allowing for an additional level of logic.
It is therefore desirable to provide gate arrangements, and particularly current sources for logic gate arrangements, which allow higher order series level gating to be accomplished.